Bang-bang phase detectors are commonly used as a part of a phase locked loop, in which a clock is derived from, and locked to, the transitions of a serial data signal.
FIG. 1 illustrates a typical Phase locked Loop (PLL) 100 of the prior art, including a bang-bang phase detector 102, a charge pump 104, a loop filter 106, and a Voltage Controlled Oscillator (VCO) 108. The VCO 108 generates a clock signal 110 which is compared with a data signal 112 in the bang-bang phase detector 102. The output of the bang-bang phase detector 102 drives the charge pump 104 whose output is filtered through the loop filter 106. The filtered output is a voltage signal 114 that controls the frequency of the VCO 108.
FIG. 2 shows a conventional implementation of a capturing part 200 of the bang-bang phase detector 102 to illustrate its operation. The capturing part 200 comprises three positive edge triggered flip-flops 202, 204, and 206, and a negative edge triggered flip-flop 208. The data signal 112 is input to the data inputs D of the first positive edge triggered flip-flop 202 and of the negative edge triggered flip-flop 208. The clock signal 110 is input to the clock inputs C of each of the flip flops 202 to 208. The data output Q of the first positive edge triggered flip-flop 202 is connected to the D input of the second positive edge triggered flip-flop 204. The data output Q of the negative edge triggered flip-flop 208 generates an edge-sampling signal 210 which is further connected to the D input of the third positive edge triggered flip-flop 206.
The Q outputs of each of the three positive edge triggered flip-flops 202, 204, and 206 generate delayed data output signals “C”, “A”, and “B” respectively which follow the data signal 112 as described next.
FIG. 3 is an exemplary timing diagram 300 to illustrate the capturing of data and data transitions of the capturing part 200 of FIG. 2. The timing diagram 300 shows waveforms of:                a serial data stream 302 which may be an instance of the data signal 112 of FIGS. 1 and 2;        a full rate clock signal 304 which may be an instance of the clock signal 110 of FIGS. 1 and 2;        a first delayed data stream 306 corresponding to the delayed output signal “C” of FIG. 2;        a second delayed data stream 308 corresponding to the edge-sampling signal 210 of FIG. 2;        a third delayed data stream 310 corresponding to the delayed output signal “A” of FIG. 2; and        a fourth delayed data stream 312 corresponding to the delayed output signal “B” of FIG. 2.        
Note that the delayed data streams 306, 310, and 312 are generated by positive edge triggered flip-flops while the delayed data stream 308 corresponding to the edge-sampling signal 210 is generated by the negative edge triggered flip-flop 208.
The serial data stream 302 is captured by the first positive edge triggered flip-flop 202 with the rising edge of the full rate clock signal 304 to generate the first delayed data stream 306 (“C”). This first delayed data stream 306 (“C”) is delayed by a further clock period with the second positive edge triggered flip-flop 204 which generates the third delayed data stream 310 (“A”). The serial data stream 302 is also captured by the negative edge triggered flip-flop 208 with the falling edge of the full rate clock signal 304 to generate the second delayed data stream 308. This second delayed data stream 308 is then sampled by the next rising clock edge with the third positive edge triggered flip-flop 204 which generates the fourth delayed data stream 312 (“B”).
In the timing diagram 300, it is assumed that the negative edges of the full rate clock signal 304 are synchronous with transitions of the serial data stream 302. The data values of the individual data bits of the serial data stream 302 are marked D1, D2, D3 etc. in the timing diagram 300. These data values are faithfully reproduced in delayed form in the first and third delayed data streams “A” and “C” respectively which are similarly marked D1, D2, D3 etc because the data bits are sampled in the center of their bit period where the data bit is stable.
Conversely, the values of the data bits of the second delayed data stream 308 are the results of sampling the serial data stream 302 at the time of the data transitions. Due to unavoidable signal jitter, sampling the data stream during a transition may result in capturing the value of the data bit just prior to the transition, or the value of the data bit following the transition. This uncertainty is indicated by the markings of the bits in the second delayed data stream 308 with E12, E23, E34 etc.
The fourth delayed data stream 312 (“B”) is the result of retiming the second delayed data stream 308 with the rising edge of the full rate clock signal 304, thus becoming clock aligned with the data streams “C” and “A” in accordance with the practice of typical bang-bang phase detector designs.
To summarize, the delayed data output signals “A”, “B”, and “C” are clock synchronous digital signals that represent the state of the input data signal (the serial data stream 302) before, at, and after each positive edge of the full rate clock signal 304 when the clock is in synchronism and phase alignment with the edges of the input data signal.
FIG. 4 shows how the clock frequency is adjusted in the PLL 100 by the conventional bang-bang phase detector 102 depending on the situation with data transitions.
The set of diagrams of FIGS. 4a to 4f illustrates six examples of the delayed output signals “A”, “B”, and “C” depending on the alignment between the full rate clock signal 304 and the data transitions. In each of the FIGS. 4a to 4f a fragment of the data signal wave form corresponding to the serial data stream 302 is shown. The data signal wave form is indicated by a solid line which may assume low and high values (“lo” and “hi”), as well as a transition between these values. Further shown in each of the FIGS. 4a to 4f is a time fragment of the full rate clock signal 304 signal “CK” with which the data signal wave form is sampled over the span of one bit period. As described in FIG. 3, sampling of the data signal wave form with the positive edges of the clock results in values of “0” and “1” of the delayed output signals “A”, and “C”, while sampling with the negative edge results in the delayed output signal “B”. The values of “A”, “B”, and “C” depend on the alignment between the clock and the transitions in the data signal wave form. These values in the vicinity of a possible transition of the data signal wave form may then be evaluated and used to determine if the frequency of the full rate clock signal 304 (the clock frequency) should be maintained, increased, or decreased.
In FIG. 4a, the value of the data signal wave form is “lo”, there is no transition, resulting in “A”=0, “B”=0, and “C”=0. No adjustment of the clock frequency is made.
In FIG. 4b, there is a positive transition of the data signal wave form from “lo” to “hi”, the transition occurring after the negative clock edge resulting in “A”=0, “B”=0, and “C”=1. The clock frequency should be increased in order to pull the data transition towards alignment with the negative clock edge as indicated by the arrow dragging the transition to the left.
In FIG. 4c, there is a positive transition of the data signal wave form from “lo” to “hi”, the transition occurring before the negative clock edge resulting in “A”=0, “B”=1, and “C”=1. The clock frequency should be decreased in order to pull the data transition towards alignment with the negative clock edge as indicated by the arrow dragging the transition to the right.
In FIG. 4d, there is a negative transition of the data signal wave form from “hi” to “lo”, the transition occurring before the negative clock edge resulting in “A”=1, “B”=0, and “C”=0. The clock frequency should be decreased in order to pull the data transition towards alignment with the negative clock edge as indicated by the arrow dragging the transition to the right.
In FIG. 4e, there is a negative transition of the data signal wave form from “hi” to “lo”, the transition occurring after the negative clock edge resulting in “A”=1, “B”=1, and “C”=0. The clock frequency should be decreased in order to pull the data transition towards alignment with the negative clock edge as indicated by the arrow dragging the transition to the left.
Lastly in FIG. 4f, the value of the data signal wave form is “hi”, there is no transition, resulting in “A”=1, “B”=1, and “C”=1. No adjustment of the clock frequency is made.
No diagram is presented to show the negative clock edge coinciding with a transition of the data signal wave form. In this event, the negative edge triggered flip-flop 208 would resolve this into “0” or “1” with a statistically equal probability of 50%. This case arises when the correct clock frequency has been achieved by the PLL. As a result, the clock frequency adjustment will continue to be either to increase or to decrease with equal probability causing some clock jitter. The loop filter 106 (see FIG. 1) is commonly used to dampen this jitter.
Numerous improvements to the basic bang-bang phase detector design have been proposed in the prior art. For example, a modified bang-bang phase detector is described in U.S. Pat. No. 5,592,125 issued to Bertrand Williams which was designed to provide an improvement in terms of the resulting transfer function and jitter performance of a PLL based on the modified bang-bang phase detector.
In the United States Patent Application 2006/0139108 of Gunter Willy Steinbach et al. a more complex PLL incorporating a bang-bang phase detector is described which was designed to be less susceptible to overshoot and charge pump leakage.
PLLs based on a bang-bang phase detector of the prior art require a VCO having a frequency to match the data rate. In receivers for very high data rates it is often inconvenient to provide such a full rate clock.
In the United States Patent Application 2004/0114702 of Daniel J. Friedman, a half-rate bang-bang phase detector is described. However, this detector is based on a tri-state design realized with a special double-edge flip-flop that can trigger on both edges of the clock signal.
While the simplicity of the bang-bang principle would make a bang-bang phase detector an advantageous choice in a PLL for a high speed data receiver, this advantage is very much diminished by the need for a corresponding high speed clock which requires significant effort, for example in terms of power.
Accordingly, there is a requirement to develop a simple bang-bang phase detector, which could be implemented with ordinary high speed logic and operated with a reference clock of a reduced frequency.